1. Field of the Invention
The present invention relates to an arithmetic unit and a data processing unit mounted in a digital signal processor and the like.
2. Description of the Prior Art
A prior art data processing unit for performing data comparison will be described below. The prior art data processing unit hereinafter described is primarily used as a special-purpose circuit when performing variable length encoding of image information, etc. after a discrete cosine transform. The prior art data processing unit has the circuitry shown, for example, in FIG. 16, in which reference character 1x is a memory (8-bit-data memory with addresses 0 to 63), 2x is a read control circuit, 3x is a zero run counter, 4x is a zero decoder, 5x is memory data, 6x is a memory read control signal, 7x is an enable signal, 8x is a zero decode signal, and 9x is a zero run count signal. Further, reference character 10x is a variable length encoder for performing variable length encoding.
Operation of the thus configured data processing unit will be described below with reference to the waveform diagram of FIG. 17 (reference characters shown correspond to those in FIG. 16). In FIG. 17, a typical memory readout address signal is depicted as the memory readout control signal 6x.
Waveform 1w in FIG. 17 is used as the operating clock (CLK) of the data processing unit of FIG. 16. The read control circuit 2x in FIG. 16 reads out the memory data 5x at the address specified by the memory readout control signal 6x when the enable signal 7x is at a high level (hereinafter referred to as H level) (in the illustrated example, addresses are generated in the order of 0, 1, 2, . . . , 63).
The zero decoder 4x decodes the memory data 5x and, when the memory data shows a value 0, sets the zero decode signal 8x to the H level. At this time, the zero run counter 3x counts up, thus counting the number of 0s occurring consecutively. When the zero decode signal 8x is at a Low level (hereinafter referred to as the L level), the zero run counter 3x shows a value 0.
The thus generated zero run count signal 9x and the zero decode signal 8x are output together with the memory data 5x; the variable length encoder circuit 10x at the following stage performs data processing using the zero run count signal 9x and memory data 5x at the time that the zero decode signal 8x is at the L level. Variable length encoding is a process in which data is compressed by treating the number of consecutive data zeros and the nonzero data following the data zeros as one set of data. Strictly speaking, quantization is performed before the variable length encoding. In the illustrated example, the zero run count signal 9x indicates the number of consecutive data zeros and the memory data 5x the nonzero data.
Since specialized circuitry, such as the zero run counter 3x and the zero decoder 4x, is used to sequentially detect and output the number of consecutive zeros and the nonzero data following the data zeros, the prior art data processing unit lacks versatility and cannot, for example, detect the number of consecutive data values other than zeros; further, when, for example, it becomes necessary to perform an addition or comparison in addition to sequentially detecting and outputting the number of consecutive data zeros and the nonzero data following the data zeros, extra circuitry for performing the addition or comparison has to be added.
Furthermore, the prior art data processing unit, when mounted as a special-purpose circuit in a digital signal processor or the like, is not able to continuously perform the data processing using the zero run count signal 9x and-memory data 5x if zeros continue to appear in the memory data. The reason is that, since data compression is performed using both the number of consecutive zeros and the nonzero data, it is not possible to produce the output of the zero run counter 3x and the output of the nonzero data in every cycle.
The prior art data processing unit has also had the problems that it lacks versatility because it is designed for performing data processing on fixed data (in the above example, data zeros), and that the processing time increases since data retrieval is performed through the entire memory even in the case of data that may be all zeros beyond a certain memory range.